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TRIDENT.TXT
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1996-01-04
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21KB
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539 lines
Trident SuperVGA
Trident TVGA8800BR 512k Only 128K banks.
TVGA8800CS 512k Has 64k banks and old/new mode
TVGA8900B 1MB
TVGA8900C 1MB
TVGA8900CL 2MB
TVGA8900D 2MB Same as 8900CL, but with a few bug corrected
(which?)
TVGA9000 Low component version
TVGA9000i Low component count. 15/16 bit DAC on chip
Clock generator on chip
9200CXr 2MB
TGUI9400CXi 2MB Clock & 24bit DAC onchip
TGUI9420DGi 2MB As 9400, but with Accelerator (BitBlt, Color Exp
Fills, Line draw and Linear Frame buffer)
TGUI9430 As 9420 + Hardware cursor
TGUI9440AGi 2MB As 9430, 16bit DAC interface and programmable
clock ??
TGUI9660XGi 64bit video memory path
TGUI9680 As 9660, but with video acc
LCD9100B Suppose these are LCD controllers, anyone seen them?
LCD9100
LX8200
Support chips:
TCK9001 Clock chip for the 8900B.
Supplies: 25.175, 28.322, 44.9, 36, 57.272, 65, 50.35, 40 MHz
TCK9002 Clock chip for the 8900C and later.
Supplies: 25.175, 28.322, 44.9, 36, 57.272, 65, 50.35, 40,
88, 98, 118.8, 108 MHz
TCK9004 Clock chip for the 8900CL and later.
Supplies: 25.175, 28.322, 44.9, 36, 57.272, 65, 50.35, 40,
88, 98, 118.8, 108, 72, 77, 80, 75 MHz
TKD8001 "ColorSync" truecolor RAMDAC
What are the specs for all the new chips?? (CX,CXi,CL,CXr,GUI...)
The Trident 8800 chips have a problem with 256 color modes,
as they always double the pixels output in 256 color mode.
Thus a 640x400 256 color mode (5Ch) actually uses a 1280x400
frame, requiring at least a multi sync monitor.
This problem is fixed on the 8900.
Apparently Trident BIOS version 3.xx or later on a 8900C will support Sierra
HiColor DACs (SC11483 or SC11487). No check is made for the existence of such
a DAC, the mode is just set as if it was present, resulting in 1024x480,
1280x480 and 1600x600 256color modes if an ordinary DAC is installed.
100h W(R/W?): Microchannel ID low/high
bit 0-15 Card ID bit 0-15
3C3h (R/W): Microchannel Video Subsystem Enable Register:
bit 0 Enable Microchannel VGA if set
3C4h index 0Bh (R): Chip Version
bit 0-7 Chip ID
1 = TR 8800BR
2 = TR 8800CS
3 = TR 8900B
4 = TVGA8900C
13h = TVGA8900C
23h = TR 9000
33h = TVGA8900CL, TVGA8900D or TVGA 9000C
43h = TVGA9000i
53h = TR 9200CXr
63h = TLCD9100B
73h = TGUI9420
83h = TR LX8200
93h = TGUI9400CXi
A3h = TLCD9320
C3h = TGUI9420DGi
D3h = TGUI9660XGi
E3h = TGUI9440AGi
F3h = TGUI9430 One source says 9420 ??
The 63h, 73h, 83h, A3h and F3h entries are still in doubt.
Note: Writing to index Bh selects old mode registers.
Reading from index Bh selects new mode registers.
Note: Writing to this register in order to force old mode registers
should be done with two 8bit writes, not one 16bit write.
3C4h index 0Ch (R/W): Power Up Mode Register 1
bit 0 Fast Decode if set, Slow if clear
1 (9000 & LCD9100) If clear 0 Wait states,
if set bit 6 determines number of wait states.
4 If set enable post port at 3C3h, at 46E8h if clear
5 (8900C) If set enables access to upper 512KB in non-paged modes
Must be clear in text and CGA modes.
(9000 & LCD9100) If set uses 2 DRAMs, 4 if clear
6 (9000 & LCD9100) If bit 1 is clear this bit determines the number
of wait states. If set 2 Wait states, 1 if clear.
5-6 (88xx and 89xx) 0=256K chip, 1 = 2 DRAMs, 2 = 4 DRAMs, 3 = 8 DRAMs.
7 If set VRAM bus setting is 16, 8 if clear
Note: This register can only be changed if New Mode Control 1 (3C4h index 0Eh)
bit 7 is set
3C4h index 0Dh (R/W): Old Mode Control 2
bit 0-2 Emulation mode
0=VGA, 3=EGA, 5=CGA,MDA,Hercules
4 Enable Paging mode if set. If set the CRTC offset (3d4h index 13h)
should be multiplied by 2, and the Display Start Address (3d4h index
0Ch & 0Dh + 1Eh bit 5 and 3C4h Old Mode index 0Eh bit 0) is in units
of 8 bytes rather than 4 (256 color modes only).
5 DRAM clock enabled if set.
3C4h index 0Dh (R/W): New Mode Control 2 (not 8800BR)
bit 0 Clock Select bit 2. Bits 0-1 are in 3CCh bits 2-3.
Clock table:
0: 25.1 75 1: 28.322 2: 44.9 3: 36
4: 57.272 5: 65 6: 50.35 7: 40
8: 88 9: 98 10: 118.8 11: 108
12: 72 13: 77 14: 80 15: 75
For the 8800 and 8900B only the first 8 clocks are available.
For the 9000i line 3 is: 8: 25.175, 9: 28.322, 10: 62.3, 11: 44.9
1-2 Divide pixel clock by: 0=1, 1=2, 2=4, 3=1.5
6 (9xxx) Clock Select bit 3. See bit 0
Note: The old/new Mode Control 1/2 registers are selected by
reading and writing the Chip version register (index Bh).
3C4h index 0Eh (R/W): Old Mode Control 1
bit 0 (8900 Only) CRTC Address bit 17. Apparently this determines in which
part of memory the display is, as the display can not cross this
line, but can be on either side. Note that in Paged Mode (3C4h Old
Mode index 0Dh bit 4 is set) this bit has no effect as 17 bits can
span the entire 1MB range.
1-2 128kb Bank number (0-3)
3 16 bit video interface if set
4 (8900C, CL, CXr, GUI9420) Clock Select bit 3.
See New mode 3C4h index Dh bit 0.
3C4h index 0Eh (R/W): New Mode Control 1 (not 8800BR)
bit 0-3 64k Bank nbr. When writing to this field XOR with 02h, when reading
from this field no XOR is needed. This is used for Trident detection.
In planar modes bits 0 and 2 form a two bit field.
4-6 Reserved
7 Must be set to update index 0Ch ???
Note: The old/new Mode Control 1/2 registers are selected by
reading and writing the Chip version register (index Bh).
3C4h index Fh (R/W): Power-up Mode 2
bit 0-3 Switch settings
4 Bus type
5 If set I/O address are at 3xxh, else at 2xxh.
6 Enable ON-Card ROM if set
7 16 bit ROM access enabled if set
3CEh index 0Eh (R/W): New Source Address Register (8900CL/D,9200 +)
bit 0-3 Bank register. If 3CEh index Fh bit 2 is clear and bit 0 is set this
is the read bank and 3C4h index Eh the write register. Note that bit
1 is inverted like 3C4h index Eh bit 1.
3CEh index 0Fh (R/W): Miscellaneous Extended Functions (8900CL/D,9200 +)
bit 0 DUAL. If set selects dual bank mode with separate read and write
bank registers. If bit 2 is set 3D9h is the read bank and 3D8h the
write bank, if bit 2 is clear 3CEh index Eh is the read bank and 3C4h
index Eh the write bank
3D8h is the combined read/write bank. Only active if bit 2 is set.
1 When set the packed pixel modes (256 or more colors) uses bits 0-1 of
the PEL panning register (3C0h index 13h) for single pixel horizontal
scrolling rather than bits 1-2 (as Standard VGA).
2 ENALTP. Set to use the alternative banking registers at 3D8h/3D9h,
clear to use the old banking registers.
?? Must be set when 3C4h index Ch bit 5 is set ??
3 If set character clocks are 16pixels wide rather than 8
3d4h index 1Eh (R/W): Module Testing Register
bit 2 Vertical interlace if set
In interlaced modes the CRTC offset (3d4h index 13h) is the number of
bytes in TWO scanlines (NOT true for the 9440AGi!).
Note that in interlaced modes the line doubling caused by index 9 bits
0-4,7 is unlikely to work, as the (even,odd) linepair is repeated
rather than each individual line causing stripes.
3 If set Load fonts from Bottom, from top if clear
4 If set the display wraps back to line 0 when the line counter reaches
512.
5 CRTC Display Start Address bit 16. Bits 0-15 are in 3d4h index Ch,Dh
7 (not 88xx) Host address bit 16. If clear bit 5 has no effect.
This does not affect 3C4h Old Mode index 0Eh bit 0.
3d4h index 1Fh (R/W): Software Programming Register
bit 0-1 (8800, 8900, 9000) Memory size 0=256k, 1=512k, 2=768k, 3=1M.
0-2 (8900CL, 9200CXr, 94xx, 9660) Memory size 0=256k, 1=512k,
2=768k, 3=1M, 4=256k, 5=512k, 6=768k, 7=2M.
4-6 (9420DGi) Monitor Type.
(9430,9440,9660) Monitor Type.
Note: This register set by software
Everex 8800 based cards have different layout, see below
3d4h index 1Fh (R/W): Scratch Register (Everex 8800 Cards)
bit 0 Paged memory mode in effect
1 Memory size 0=256k, 1=512k
2 Analog monitor attached
3 44.9 MHz oscillator present
Note: This register is set by software.
3d4h index 21h (R/W): Configurable Linear Addressing Register (94xx)
Bit 0-3 LAWB0-3. Bits 20-23 of the Linear Aperture address
4 LAWS. If set the aperture is 2Mbytes, if clear 1MB.
5 ENLA. Set to enable Linear aperture.
6-7 Linear Aperture Address bits 24-25
3d4h index 22h (R): CPU Latch Read Back
bit 0-7 Data Latch value for current read plane.
3d4h index 23h (R/W):
bit 0-5 ??
3d4h index 24h (R): Attribute State Read Back
bit 0-6 Reserved
7 Attribute Controller State
If set the next write to 3C0h will go to the data
register, if clear to the index register.
3d4h index 26h (R): Attribute Index Read Back
bit 0-7 Attribute Index Register value
3d4h index 27h (R/W): (8900CL/D +)
bit 0-1 Display Start Address bit 17-18. Bit 16 is in index 1Eh bit 5.
3d4h index 28h (R/W):
bit 0-7 ??
3d4h index 29h (R/W): (8900CL/D +)
bit 0 Connected to the RS2 input on the DAC ?.
1 ??
4 CRTC offset bit 8 ??
3d4h index 2Ah (R/W):
bit 6 ??
3d4h index 2Fh
bit 0-2 ?
4 ?
5-6 ?
3d4h index 36h
bit 1 ?
7 ?
3d4h index 38h (9440)
bit 2-3 Pixel depth?. 1: 15/16 bit modes, 2: 24bit modes, 0: all other modes
3d4h index 40h W(R/W): (9440)
bit 0- Hardware Cursor *tal Location
3d4h index 42h W(R/W): (9440)
bit 0- Hardware Cursor *tal Location
3d4h index 44h W(R/W): (9440)
bit 0- Location of hardware cursor map in video memory in units of 1Kb
The hardware cursor map appears to be a 32x32x2 or 64x64x2 bitmap
organised in lines of 8 or 16 bytes, each having first 4 bytes
(32pixels) of AND data and then 4bytes XOR data (windows style).
The cursor displayed also depends on the cursor style (3d4h index 50h
bit 6).
AND: XOR: Style: Resulting screen:
0 0 0 Palette index 0 ?
1 0 0 Screen data (Transparent cursor)
0 1 0 Palette index 255 ?
1 1 0 Inverted screen (XOR cursor)
0 0 1 Screen data (Transparent cursor)
1 0 1 Palette index 0 ?
0 1 1 Screen data (Transparent cursor)
1 1 1 Palette index 255 ?
3d4h index 46h (R/W): (9440)
bit 0-5 Cursor Horizontal hotspot. The position (in pixels from the left) of
the cursor hotspot within the 32x32 or 64x64 map. The displayed cursor
starts at the hotspot and ends 32/64 pixels from the left edge (i.e.
it does not wrap to the next line).
3d4h index 47h (R/W): (9440)
bit 0-5
3d4h index 50h (R/W): (9440)
bit 0 Set for 64x64 cursor, clear for 32x32 cursor
6 Clear for Cursor Style 0 (Windows?), set for Cursor Style 1 (X11?)
7 Enable hardware cursor if set
3D8h (R/W): Destination Segment Register (8900CL/D,9200 +)
bit 0-4 Bank number in 64k units. If 3CEh index Fh bit 0 is set this is the
write bank, if not the combined read/write bank.
This register is only active if 3CEh index Fh bit 2 is set.
3D9h (R/W): Source Segment Register (8900CL/D,9200 +)
bit 0-4 If 3CEh index Fh bit 0 is set this is the read bank.
This register is only active if 3CEh index Fh bit 2 is set.
Note: Ferraro (in Programmer's Guide to... 3rd edition) documents the
accelerator registers at 21xAh for the later Tridents, however so far
I have been unable to verify this.
43C6h W(R/W): Memory Clock (9440)
bit 0-15 Selects the memory clock. 2C6h = 50MHz, 307h = 58MHz, 87h = 64MHz
8Eh = 75MHz
Note: 3C4h index Eh (new) bits 1 & 7 must be set to update this register
43C8h W(R/W): Video Clock (9440)
bit 0-15 Selects the video clock when 3C2/Ch bits 2-3 = 2.
Note: 3C4h index Eh (new) bits 1 & 7 must be set to update this register
46E8h (R): Video Subsystem Enable Register
bit 3 Enable VGA if set
The memory mapped registers appears to be mapped at BFF00h (how to enable
them ?). Probably only exists on the 9440 and later (9420?)
M+20h (R?)
bit 5 Set when the graphics engine is busy?
6 Set if ? Data transfers should wait for it to clear?
7 Set when ?
M+22h (R/W):
bit 0-? 9 for non-8bit modes, 4 for 8bit modes (<=1024), 8 for other modes
M+24h (R/W):
bit 0-2 Write 1 to start a Blit, 4 to start a line draw ?
M+27h (R/W):
bit 0-7 Raster op (=Bits 16-23 of the Windows ROP3).
M+28h W(R/W):
bit 2 Set when using pattern ??
5 Set when using pattern ??
6 ??
8 If set the Blit moves bottom-to-top (decreasing address), if clear
it is top-to-bottom (increasing address).
9 If set the Blit moves right-to-left (decreasing address), if clear
it is left-to-right (increasing address).
14 Set for solid fills ??
M+2Bh (R/W):
bit 0-2 Offset into the pattern ?
M+2Ch W(R/W):
bit 0- Background color
M+30h W(R/W):
bit 0- Foreground color
M+34h W(R/W):
bit 0-15 Address of ?pattern? in units of 64bytes
M+38h W(R/W):
bit 0- Destination starting X-coordinate
M+3Ah W(R/W):
bit 0- Destination starting Y-coordinate
M+3Ch W(R/W):
bit 0- Source starting X-coordinate
M+3Eh W(R/W):
bit 0- Source starting Y-coordinate
M+40h W(R/W):
bit 0- Width of the Blit area in pixels
M+42h W(R/W):
bit 0- Height of the Blit area in scanlines
M+44h
M+46h W(R/W):
Bank selection:
Trident VGAs (except 8800BR) can operate in 2 different modes:
Old Mode, with a 128k window to display memory at A000h - BFFFh
and New Mode, with a 64k window to display memory at A000h - AFFFh.
Old/New mode is selected by reading/writing the Chip Version Register
(3C4h index 0Bh).
Each mode has its own registers at 3C4h index 0Dh and 0Eh.
ID Trident VGA:
wrinx($3C4,$B,0); {Force old_mode_registers}
chp:=inp($3C5); {Read chip ID and switch to new_mode_registers}
old:=rdinx($3C4,$E);
outp($3C5,0);
value:=inp($3C5) and $F;
outp($3C5,old);
if value=2 then
begin
outp($3C5,old xor 2);
case chp of
1:Trident TR8800BR;
2:Trident TR8800CS;
3:Trident TR8900;
4,$13:Trident TR8900C;
$23:Trident TR9000;
$33:Trident TR8900CL or D;
$43:Trident TR9000i;
$53:Trident TR8900CXr
$63:Trident LCD9100B;
$83:Trident LX8200;
$93:Trident TVGA9400CXi
$A3:Trident LCD9320;
$73,$F3:Trident GUI9420;
end;
end
else if (chp=1) and testinx2($3C4,$E,6) then
Trident TVGA 8800BR {Haven't tested this yet}
Video Modes:
50h T 80 30 16 (8x16)
51h T 80 43 16 (8x11)
52h T 80 60 16 (8x8)
53h T 132 25 16 (8x14)
54h T 132 30 16 (8x16)
55h T 132 43 16 (8x11)
56h T 132 60 16 (8x8)
57h T 132 25 16 (9x14)
58h T 132 30 16 (9x16)
59h T 132 43 16 (9x11)
5Ah T 132 60 16 (9x8)
5Bh G 800 600 16 PL4
5Ch G 640 400 256 P8
5Dh G 640 480 256 P8
5Eh G 800 600 256 P8 (Undocumented on 8800)
5Fh G 1024 768 16 PL4
60h G 1024 768 4 8900 Only
61h G 768 1024 16 PL4
62h G 1024 768 256 P8 8900 Only
63h G 1280 1024 16 PL4 Which chip/BIOS rev ?
64h G 1280 1024 256 P8 8900CL only
6Ah G 800 600 16 PL4 Newer boards
6Bh G 320 200 16m P24 TVGA9000i+
6Ch G 640 480 16m P24 8900CL+
6Dh G 800 600 16m P24 8900CL+
70h G 512 480 32K P15 89xx with Sierra DAC
71h G 512 480 64K P16 89xx with Sierra DAC
74h G 640 480 32K P15 89xx with Sierra DAC
75h G 640 480 64K P16 89xx with Sierra DAC
76h G 800 600 32K P15 89xx with Sierra DAC
77h G 800 600 64K P16 89xx with Sierra DAC
78h G 1024 768 32K P15 8900CL with Sierra DAC
79h G 1024 768 64K P16 8900CL with Sierra DAC
7Eh G 320 200 32K P15 TVGA9000i
7Fh G 320 200 64K P16 TVGA9000i
ZyMOS POACH51 modes:
60h G 960 720 16 PL4
61h G 1280 640 16 PL4
62h G 512 512 256 P8
63h G 720 540 16 PL4
64h G 720 540 256 P8
6Ah G 800 600 16 PL4
Everex Viewpoint use Everex modes.
Note: The TVGA9000i has an on-chip DAC with 32k/64k capability.
The BIOS on the card I have (BIOS version D3.51) doesn't
seem to handle the Hi/True color modes correctly.
I have managed to get the 320x200 32k/64k modes working by programming
the DAC command register directly, but the 512x480 modes and the 320x200
16m mode still doesn't work
Bios extensions:
----------1000-------------------------------
INT 10 - VIDEO - SET VIDEO MODE
AH = 00h
AL = mode number
Return: AH = Status of call: (Trident Super VGA Chips)
Trident 8800 Trident 8900
00h Successful do
80h Fail. Wrong switch do
81h Insufficient Video do
Memory.
82h The 36MHz crystal Mode not supported
cannot support the mode
83h The 40MHz crystal Mode not supported
cannot support the mode.
84h The 44.9MHz crystal Mode not supported
cannot support the mode.
85h Dead or no crystal
86h Wrong CRTC base for dual screen
87h Text mode not supported
Note: The return code appears to be unsupported on some newer Trident
card, i.e. 9440AGi
----------1012-BL11------------------------------
INT 10 - VIDEO - Trident BIOS - Get BIOS Info
AH = 12h
BL = 11h
Return: AL = 12h if function supported
ES:BP -> BIOS info structure:
Offset: Size: Description:
00h BYTE ??? (=0)
01h BYTE OEM Code (00h for original Trident)
02h WORD ID ?? (1073h for 8800BR, 1074h for 8800CS,
1090h for 8900C or 9000i
04h 8 BYTEs BIOS date ('mm/dd/yy')
0Ch WORD ???
0Eh 8 BYTEs BIOS Version (' C3-128 ', ' C3-129 ',
' D3.51 ').
----------1012-BL12------------------------------
INT 10 - VIDEO - Trident BIOS - GET VIDEO RAM SIZE
AH = 12h
BL = 12h
Return: AL = 12h if function supported
AH = number of 256K banks of RAM installed
----------101200-BL14----------------------------
INT 10 - VIDEO - Trident LOCKFIFO - Get FIFO state
AX = 1200h
BH = 14h
Return: CX = FIFO state
Note: Implemented by the LOCKFIFO.COM utility
----------101201-BL14----------------------------
INT 10 - VIDEO - Trident LOCKFIFO - Get FIFO state
AX = 1201h
BH = 14h
CX = FIFO state (0..FFh, FFh = disabled)
Note: Implemented by the LOCKFIFO.COM utility
